ACM-024 Additional constraint for DDR2SDRAM module (ALTMEMPHY)

Last Updated: Thursday, 07 September 2017


To implement ALTMEMPHY for ACM-024 (Cyclone IV GX) 's DDR2SDRAM, you need to add some additional constraints.

Here is an example for Nios Processor implementation with "DDR2 SDRAM Controller with ALTMEMPHY" component.

Quartus II Version 11.0 SP2
DDR2 SDRAM Controller with ALTMEMPHY v11.0 (Build 208)


TCL script files generated by ALTMEMPHY

 ALTMEMPHY component generates some TCL script files when you generate Nios design.
Run a TCL file, "altmemddr_0_pin_assignments.tcl" in QuartusII.


Add constraints

 In "Assignment Editor", you can see that many constraints are added by the TCL script.
"Output Enable Group" constraints are applied to DQ and DM groups, so please add "clk pins" into the group.

Then, your design will be implemented successfully.


Errors without the additional constrains

For your information, you will see errors as below without the additional constraints.

Error: Cannot place pin mem_dq_to_and_from_the_altmemddr_0[6] to location W9
Error: Can't place VREF pin W10 (VREFGROUP_B3_N1) for pin mem_dq_to_and_from_the_altmemddr_0[6] of type bi-directional with SSTL-18 Class I I/O standard at location W9
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin W10 (VREFGROUP_B3_N1) is used on device EP4CGX50CF23C8 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out


Design Files

 We do not offer sample design files. If you have any questions, please feel free to contact us https.


[kw] 2012-02-27 ACM-024 CycloneIV DDR2SDRAM ALTMEMPHY QuartusII

[ ]



© HuMANDATA LTD. - Intel (Altera) & Xilinx FPGA Boards manufacturer in Japan - 2017 Sitemap